The present invention relates to semiconductor devices, and more specifically, to nanowire field effect transistor (FET) devices.
The use of non-planar semiconductor devices such as, for example, Fin FET devices (i.e., FinFETs) is desirable due the ability to reduce the overall size of the semiconductor device. The fabrication of non-planar semiconductor devices such as, for example, gate-all-around nanowire FET devices, typically utilizes a semiconductor-on-insulator (SOI) substrate to reduce parasitic device capacitance. SOI substrates typically include a bulk substrate, a buried insulator layer located atop the bulk substrate, and a semiconductor-on-insulator (SOI) layer located atop the buried insulator layer.
Nanowire FET devices have become a popular non-planar semiconductor device due to their improved channel electrostatics control. Formation of nanowire FET devices typically includes forming one or more semiconductor fins atop a SOI layer and then undercutting the fins located in the gate region to form suspended fins, typically referred to as suspended nanowires. The undercutting process allows access to the complete surface of the suspended nanowires. In this manner, a gate electrode formed in the gate region contacts all sides of the nanowire achieving a gate-all-around configuration which improves channel electrostatics control. However, conventional undercutting processes used to form the suspended nanowires in the gate region have tendency to etch in an isotopic manner which laterally extends the gate region. In some instances, the lateral undercut beneath a raised source/drain region which can cause an electrical short circuit path between the gate electrode formed in the gate region and epitaxial material used to form raised source/drain regions of the device.